View PEM002_8333513.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev the PEM002 is a highly integrated millimeter wave receiver that covers the 60 ghz global unlicensed spectrum allocations packaged in a standard waveguide module. receiver architecture is a double conversion, sliding if with wide bandwidth capability through the conversion chain down to baseband. the i/q analog interface along with built-in am and fm detectors provides for fexibility in design and applications. the receiver incorporates a complete waveguide interface with low-loss transition between the chip and the wr15 waveguide port. the integrated package is small and lightweight, with a simple to use multi-pin st4 connector for power, reference clock, digital control port and baseband signals. either of two reference clocks can be used for setting 540 mhz or 500 mhz channel spacing. features: ? complete millimeter wave receiver ? wr-15, ug-385/u fange ? operates in the 57 to 66 ghz unlicensed band ? 6 db noise fgure ? up to 1.8 ghz modulation bandwidth ? i/q analog baseband interface ? integrated am/ask and fm/fsk detectors ? on chip synthesizer covers 57 to 64.8 ghz ? 500 mhz or 540 mhz step size ? 285.714 mhz clock for 500 mhz step size ? 308.572 mhz clock for 540 mhz step size ? power, control, signals on st4 connector ? temperature sensor applications ? 802.11ad: 58.32, 60.48, 62.64, 64.80 ghz ? 802.11aj: 59.94, 61.02, 62.10, 63.18 ghz ? any channel (500 mhz or 540 mhz) 57-64.8 ghz ? multi-gbps digital communications ? hd video transmission ? millimeter wave radar ? millimeter wave radiometry ? millimeter wave imaging ? microwave temperature profling (mtp) ? development for 802.11ad and 802.11aj ? ate equipment for 60 ghz manufacturing test
2 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev .354" (9.00 mm) g g 1.057" (26.85 mm) wr-15 ug-385/u flange .750" (19.05 mm) .792" (20.12 mm) g g .315" (8.00 mm) samtec st4-20 connector .591" (15.00 mm) .394" (10.00 mm) pin 1 figure 1 PEM002 mechanical dimensions
3 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev 2.7v 2.7v 2.7v 2.7v 2.7v 2.7v 1.5v 1.5v 2.7v out_qm 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 out_qp out_im out_ip refclkm refclkp q1_b_c q1_e reset enable clock data scanout vdd vdd vcc samtec st4-20 mating connector: samtec ss4-20-3.00-l-d-k-tr vcc vcc vcc vcc vcc vcc g g pin 1 figure 2 PEM002 interface connector pinout
4 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 1 performance specifcations* parameter unit comment i/q balance phase i/q balance amplitude min typ max frequency range 57.0 64.8 ghz channel spacing 540 mhz 308.571 mhz reference channel spacing 500 mhz 285.714 mhz reference gain, max gain, range 67 65 db db gain, step size 1.25 db 53 70 image rejection >35 db input ip3 -27 dbm input p1db at max gain -36 dbm at min gain sideband suppression 27 dbc noise figure 6 db at max gain phase noise @ 100 khz -72 dbc/hz phase noise @ 1 mhz -86 phase noise @ 10 mhz -111 phase noise @ 100 mhz -125 phase noise @ 1 ghz -127 dbc/hz dbc/hz dbc/hz dbc/hz pll loop bandwidth 200 khz 3 degrees 1 db *test conditions: reference frequency 308.571 mhz temperature 25c input signal level -65 dbm if bandwidth max output impedance 50 ohms, 4 output ports: i +/- and q +/- (100 ohm differential) output signal level referenced to single 50 ohm output for gain specifications modulation bandwidth max bw setting, double-sided at 3 db 1.8 ghz
5 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 2 recommended operating conditions description unit power supplies v 1 reference clock power level specified at 100 ohms differential 2 baseband voltage at each of the 4 baseband outputs (i +/-, q +/-) 3 temperature sensor is a 2n3904 npn transistor die connected as a diode junction min typ max name vcc vdd st4 pin # 8,22,24,26, 28,30,32 10,34 2.7 2.565 2.835 1.5 1.425 1.575 v serial control port logic high serial control port logic low data clock enable reset scanout data clock enable reset scanout 38 36 39 37 40 38 36 39 37 40 1.3 1.575 1.0 0.1 0.33 -.05 v v reference clock 1 refclkm refclkp 25 27 0 -5 3 dbm out_qm out_qp out_im out_qp i and q baseband 2 1 3 7 9 operating temperature -40 85 c temperature sensor 3 q1_e q1_b_c 31 33 10 100 400 mvpp vcc 2.7v supply current icc idd 225 ma 8 ma vdd 1.5v supply current t a serial control port speed 100 mhz
6 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 3 absolute maximum ratings description power supplies max name vcc vdd st4 pin # 8,22,24,26, 28,30,32 10,34 2.85 v 1.6 v serial control port logic high serial control port logic low data clock enable reset 1 scanout data clock enable scanout 38 36 39 37 40 38 36 39 37 40 1.575 -.05 reference clock refclkm refclkp 25 27 5 dbm out_qm out_qp out_im out_qp i and q baseband 1 3 7 9 operating temperature -40 to 85 c storage temperature t a 750 mvpp power dissipation 760 mw t s -55 to 150 c gnd 50 mv 5,11,17,23,29,35 p d reset 1 1 assertion of reset, active high, asynchronously resets all registers
7 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev receiver architecture the PEM002 receiver uses a double conversion superheterodyne architecture with a sliding if. the if frequency is at 1/7 the rf carrier frequency, and the vco is at 2/7 the rf carrier frequency. the lo is 3x the vco frequency. the lo and if are generated from a built-in synthesizer that has a step size at the rf carrier frequency of either 500 mhz or 540 mhz depending upon which reference clock frequency is used. the 540 mhz step size uses a 308.571 mhz reference, and the 500 mhz step uses a 285.714 mhz frequency. the ieee channels for 802.11ad and 802.11aj are supported when the 540 mhz step size is used. an rf signal in the range of 57 to 64.8 ghz is coupled to the lna via the low-loss wr15 waveguide port. the lo is mixed with the rf signal after the lna and down converted the if signal in the 8 to 9 ghz range. a notch flter attenuates the image frequency. the if signal is fltered with a variable gain amplifer and flter with approximately 20 db range, which is then fed into the quadrature mixers which down converts directly to baseband. there are also selectable am and fm detectors for non-coherent modulation schemes. additional variable gain and fltering are available in the baseband amplifer section which follows the i/q mixers and detectors. the overall phase noise and i/q balance specifcations are suffcient for up to 16 qam operation. confguration and settings are controlled through a digital serial interface port. the block diagram below shows the various stages and circuits in the module. var if filter if vga synthesizer 57.0 to 64.8 ghz 0.5 or 0.54 ghz step serial control registers +1.5 +2.7 0o 90o fm det am det div x3 2 bb vga var bb filter bb vga var bb filter wr-15 waveguide ug-385/u flange refclkp refclkm enable clock data scanout reset out_qm out_qp out_im out_ip lna figure 3 PEM002 block diagram
8 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev synthesizer design the PEM002 receiver uses a double conversion superheterodyne architecture with a sliding if. the if frequency is at 1/7 the rf carrier frequency, and the vco is at 2/7 the rf carrier frequency. the lo is 3x the vco frequency. the tables below show the rf carrier, if, vco and lo for the frequency range from 57 ghz to 64.80 ghz at 540 mhz and 500 mhz channel spacing respectively. the reference clock for the synthesizer at 540 mhz spacing is 308.571 mhz; for 500 mhz spacing it is 285.714 mhz. the loop bandwidth of the synthesizer phase lock loop is 200 khz. 540 mhz spacing 500 mhz spacing f rf if vco lo 57.24 8.177 16.354 49.063 57.78 8.254 16.509 49.526 58.32 8.331 16.663 49.989 58.86 8.409 16.817 50.451 59.40 8.486 16.971 50.914 59.94 8.563 17.126 51.377 60.48 8.640 17.280 51.840 61.02 8.717 17.434 52.303 61.56 8.794 17.589 52.766 62.10 8.871 17.743 53.229 62.64 8.949 17.897 53.691 63.18 9.026 18.051 54.154 63.72 9.103 18.206 54.617 64.26 9.180 18.360 55.080 64.80 9.257 18.514 55.543 f rf if vco lo 57.00 8.143 16.286 48.857 57.50 8.214 16.429 49.286 58.00 8.286 16.571 49.714 58.50 8.357 16.714 50.143 59.00 8.429 16.857 50.571 59.50 8.500 17.000 51.000 60.00 8.571 17.413 51.429 60.50 8.643 17.286 51.587 61.00 8.714 17.429 52.286 61.50 8.786 17.571 52.714 62.00 8.857 17.714 53.143 62.50 8.929 18.587 53.571 63.00 9.000 18.000 54.000 63.50 9.071 18.143 54.429 64.00 9.143 18.286 54.857 figure 4 synthesizer rf, if, vco and lo frequencies
9 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev digital control registers and serial interface protocol - write operation the PEM002 is confgured via the serial control port which transfers data synchronously to or from (write or read operation) a register location. register locations are organized into 16, byte-wide (8-bit) locations. the register locations are written to or read from one byte at a time as shown in figures 5 and 6 respectively. figure 5 shows the sequence of the digital control signals for the enable, clock and data input pins (st4 connector, pins 39, 36 and 38 respectively) to write a single byte into the control register. after the enable signal goes low, the frst of 18 data bits (bit 0) is placed on the data pin, and 2 ns or more after the data signal stabilizes, the clock signal goes high which clocks in data bit 0. the data signal must remain stable for at least 2 ns after the rising edge of the clock. the signal levels are 1.5v cmos, 50 k impedance, with a maximum clock rate of 100 mhz. a write operation requires an 18 bit feld associated with 18 clock pulses as shown in figure 5. the 18 bit feld contains the 8-bit data (lsb is clocked in frst), followed by the byte address (byte 0 through byte 15, 000000 to 001111, lsb frst, only 4 of the 6 bits are used with the two msbs set to 0), the read/write (r/w) bit (write = 1), and the module address which distinguishes between a transmitter module and receiver module (for the PEM002 receiver, rx module = 111). after clock pulse 17 (18 total pulses), the enable signal is returned to a high state to load the register byte into the module. the clock signal must be stable in the low state at least 2 ns prior to the rising edge of the enable signal. enable clock 0 1 2 17 data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 data lsb msb byte address lsb msb r/w lsb msb tx/rx module figure 5 write operation timing diagram
10 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev digital control registers and serial interface protocol - read operation figure 6 shows the sequence of control signals at the enable, clock and data pins to read a single byte at a register location. a read operation requires a 27 bit feld: the frst 18 bits are used to clock in the bits on the data input pin. the frst 8 bits during a read operation are dont care bits as they are placeholders for the 8-bit byte data which would be present during a write operation. the following 10 bits are composed of the byte address (byte 0 through byte 15, 000000 to 001111, lsb frst, only 4 of the 6 bits are used with the two msbs set to 0), the read/write (r/w) bit (read = 0), and the module address which distinguishes between a transmitter module and receiver module (for the PEM002 receiver, rx module = 111). after clock pulse 17 (18 total pulses), the enable signal is returned to a high state while the clock signal is low, then a single clock pulse (pulse 18) is sent during the enable signal high period. the enable signal then returns to the low state while the clock signal is low. at each of the subsequent 8 clock pulses, the 8-bit data from the specifed register location is available at the scanout pin, lsb frst. note that the data signal must remain in the low state during the period from clock pulse 18 through 26. following clock pulse 26, the enable signal goes high while the clock signal is low to end the read operation. enable clock 0 1 2 17 data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 lsb msb lsb msb lsb msb scan out 0 1 2 3 4 5 6 7 26 read data 18 data byte address r/w tx/rx module lsb msb figure 6 read operation timing diagram
11 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 4.1 register byte functions bit name byte 0 7 ask_pwrdn bbamp_pwrdn_i 6 5 4 3 2 1 0 bbamp_pwrdn_q divider_pwrdn if_bgmux_pwrdn ifmix_pwrdn_i ifmix_pwrdn_q ifvga_pwrdn active high to power down ask demodulator active high to power down i-channel baseband amplifier active high to power down q-channel baseband amplifier active high to power down local oscillator divider active high to power down one of three on-chip refs (if) and associated mux active high to power down i-channel if to baseband mixer active high to power down q-channel if to baseband mixer active high to power down if variable gain amplifier byte 1 function 7 6 5 4 3 2 1 0 byte 2 ipc_pwrdn lna_pwrdn rfmix_pwrdn tripler_pwrdn bbamp_atten1_0 7 6 5 4 3 2 1 0 bbamp_attenfi_0 bbamp_selask bbamp_sigshort bbamp_atten1_1 active high to power down module current reference generator active high to power down low noise amplifier and reference active high to power down rf to if mixer active high to power down frequency tripler first baseband attenuator: bits <2:3> 11 = 18 db; 10 = 12 db; 01 = 6 db; 00 = 0 db bbamp_atten2_0 bbamp_atten2_1 second baseband attenuator: bits <0:1> 11 = 18 db; 10 = 12 db; 01 = 6 db; 00 = 0 db bbamp_attenfi_1 bbamp_attenfi_2 bbamp_attenfq_0 bbamp_attenfq_1 bbamp_attenfq_2 i channel baseband fine attenuator: bits <5:7> 101 = 5 db; 100 = 4 db; 011 = 3 db; 010 = 2 db; 001 = 1 db; 000 = 0 db q channel baseband fine attenuator: bits <2:4> 101 = 5 db; 100 = 4 db; 011 = 3 db; 010 = 2 db; 001 = 1 db; 000 = 0 db active high to switch the ask detector into the i channel baseband amplifier active high to short the inputs to the i and q channel baseband amplifiers
12 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 4.2 register byte functions bit name byte 3 7 bbamp_selbw_0 6 5 4 3 2 1 0 bg_monitor_sel_1 bg_monitor_sel_0 if_refsel lna_refsel reserved: bits <3:0> = 0011 for normal operation byte 4 function 7 6 5 4 3 2 1 0 byte 5 ifvga_bias_2 7 6 5 4 3 2 1 0 ifvga_vga_adj_3 if vga bias and if filter alignment; bits <7:0> = 1001111x for normal operation not used rfmix_tune_3 if vga gain control bits; bits <7:4> = 0000 highest gain, 1111 lowest gain if filter alignment in the rf mixer; bits <3:0> = 1111 for normal operation bbamp_selbw_1 baseband amplifiers low pass filter corner: bits <6:7> 00 = 1.4 ghz; 01 = 500 mhz ; 11 = 300 mhz; 00 = 200 mhz baseband amplif iers high pass filter corner: bits <4:5> 00 = 30 khz; 01 = 300 khz ; 10 = 1.5 mhz bbamp_selhp_0 bbamp_selhp_1 ifvga_bias_1 ifvga_bias_0 ifvga_tune_4 ifvga_tune_3 ifvga_tune_2 ifvga_tune_1 ifvga_vga_adj_2 ifvga_vga_adj_1 ifvga_vga_adj_0 rfmix_tune_2 rfmix_tune_1 rfmix_tune_0 attenuation 1.25 db/step, 20 db maximum
13 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 4.3 register byte functions bit name byte 6 7 tripler_bias_13 6 5 4 3 2 1 0 byte 7 function 7 6 5 4 3 2 1 0 byte 8 7 6 5 4 3 2 1 0 lna_bias_2 fm_pwrdn if vga gain control bits; bits <7:4> = 0000 highest gain, 1111 lowest gain if filter q in the vga amplifier; bits <2:0> = 000 for highest q and gain frequency tripler bias (upper 8 bit portion): bits <7:0> = 10111111 default bbamp_sel_fm ifvga_q_cntrl_2 tripler_bias_12 tripler_bias_11 tripler_bias_10 tripler_bias_9 tripler_bias_8 tripler_bias_7 tripler_bias_6 tripler_bias_5 tripler_bias_4 trip ler_bias_3 tripler_bias_2 tripler_bias_1 tripler_bias_0 frequency tripler bias (lower 6 bit portion): bits <7:2> = 011011 default active high to switch the fm detector into the q channel baseband amplifier active high to power down fm detector lna_bias_1 lna_bias_0 not used not used ifvga_q_cntrl_1 ifvga_q_cntrl_0 not used; bits <4:3> = xx for reduced q and wider bandwidth, bits <2:0> = 001,100,101 ,111 in seque nce
14 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 4.4 register byte functions bit name byte 9 7 not used 6 5 4 3 2 1 0 byte 10 function 7 6 5 4 3 2 1 0 byte 11 7 6 5 4 3 2 1 0 synthesizer divider ratio bits 3:0 (see tables 5.1 and 5.2) not used: bits <7:0> = xxxxxxxx rdacin_5 vco amplitude dac; bits<7:2> = 111100 for normal operation synthesizer reset; bit <1> = 0 for normal operation synthesizer divider ratio bit 4 (see tables 5.1 and 5.2) band_2 rfseldiv vco band tuning bits 2:0 (see tables 5.1 and 5.2) reserved; bit <0> = 1 for normal operation not used not used not used not used not used not used not used rdacin_4 rdacin_3 rdacin_2 rdacin_1 rdacin_0 synreset divratio_4 divratio_3 divratio_2 divratio_1 divratio_0 band_1 band_0
15 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 4.5 register byte functions bit name byte 12 7 6 5 4 3 2 1 0 byte 13 function 7 6 5 4 3 2 1 0 byte 14 7 6 5 4 3 2 1 0 pd_cal cpbias_2 cpbias_1 cpbias_0 synthesizer charge pump bias; bits <7:5> = 010 for normal operation vrsel_3 vrsel_2 vrsel_1 vrsel_0 refselvco synthesizer lock detector window width; bits <4:1> = 1111 for normal operation reserved; bit <0> = 1 for normal operation muxref div_4 en_dc ini pd_div_15 pd_div_27 pd_qp pd_vco reserved; bit <7> = 1 for normal operation enable synthesizer divider bit 4; bit <6> = 0 for normal operation synthesizer reference input dc coupling; bit <5> = 0 for normal operation reserved; bit <4> = 0 for normal operation active high to power down 1.5v circuits in synthesizer divider active high to power down 2.7v circuits in synthesizer divider active high to power down synthesizer charge pump active high to power down synthesizer vco active high to power down vco calibration; bit <7> = 0 for no rmal operation muxout multiplexer control for ability to read byte 15; bit <6> = 1 for normal operation pdcalc15 active high to power down vco alc; bit <5> = 1 for normal operation pload active high to load adjustment of vco; bit <4> = 1 for normal operation wide_1 wide_2 control for vco alc loop; bits <3:2> = 01 for normal operation slew_1 slew_0 slew rate control of sub-integer n divider; bits <1:0> = 10 fo r normal operation
16 technical data sheet click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 4.6 register byte functions table 4.6 register byte functions bit name byte 15 7 comp_p 6 5 4 3 2 1 0 function reserved (read only) rdacmsb_2 comp_n synthesizer lock indication (read only): bits <7:6> = 01 locked, = 11 above window, = 00 below window, = 10 disallowed indicating error rdacmsb_1 rdacmsb_0 rdacmux_0 rdacmux_1 rdacmux_2 table 5.1 540 mhz channels channel divider 57.24 10101 byte 10 001 band 1 11110001 11110001 byte 11 57.78 58.32 58.86 59.40 59.94 60.48 61.02 61.56 62.10 62.64 63.18 63.72 64.26 2 64.80 2 10100 10011 10010 10001 10000 11111 00000 00001 00010 00011 00100 00101 00110 00111 001 010 010 011 011 100 100 101 101 110 110 111 111 111 01010011 01000011 00110101 00100101 00010111 00000111 11111001 00001001 00011011 00101011 00111101 01001101 01011111 01101111 01111111 11110001 11110001 11110001 11110001 11110001 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 reference: 308.571 mhz note 1: band setting typical, may change from module to module and temperature. note 2: operation above 64 ghz not guaranteed over full operating temperature range. channel divider 57.0 00001 byte 10 000 band 1 11110000 11110000 byte 11 57.5 58.0 58.5 59.0 59.5 60.0 60.5 61.0 61.5 62.0 62.5 63.0 63.5 64.0 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 001 001 010 010 011 011 100 100 101 101 110 110 111 00010001 00100001 00110011 01000011 01010101 01100101 01110111 10000111 10011001 10101001 10111011 11001011 11011101 11101101 11111111 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 referenc e: 285.714 mhz note 1: band setting typical, may change from module to module and temperature.
17 technical data sheet PEM002 60 ghz receiver (rx) waveguide module PEM002 rev table 5.1 500 mhz channels channel divider 57.24 10101 byte 10 001 band 1 11110001 11110001 byte 11 57.78 58.32 58.86 59.40 59.94 60.48 61.02 61.56 62.10 62.64 63.18 63.72 64.26 2 64.80 2 10100 10011 10010 10001 10000 11111 00000 00001 00010 00011 00100 00101 00110 00111 001 010 010 011 011 100 100 101 101 110 110 111 111 111 01010011 01000011 00110101 00100101 00010111 00000111 11111001 00001001 00011011 00101011 00111101 01001101 01011111 01101111 01111111 11110001 11110001 11110001 11110001 11110001 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 reference: 308.571 mhz note 1: band setting typical, may change from module to module and temperature. note 2: operation above 64 ghz not guaranteed over full operating temperature range. channel divider 57.0 00001 byte 10 000 band 1 11110000 11110000 byte 11 57.5 58.0 58.5 59.0 59.5 60.0 60.5 61.0 61.5 62.0 62.5 63.0 63.5 64.0 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 001 001 010 010 011 011 100 100 101 101 110 110 111 00010001 00100001 00110011 01000011 01010101 01100101 01110111 10000111 10011001 10101001 10111011 11001011 11011101 11101101 11111111 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 referenc e: 285.714 mhz note 1: band setting typical, may change from module to module and temperature. 60 ghz receiver (rx) waveguide module from pasternack enterprises has same day shipment for domestic and international orders. our rf, microwave and fber optic products maintain a 99% availability and are part of the broadest selection in the industry. click the following link (or enter part number in search on website) to obtain additional part information including price, inventory and certifcations: 60 ghz receiver (rx) waveguide module PEM002 url: http://www.pasternack.com/60-ghz-receiver-module-PEM002-p.aspx
1 8 ? 2013 pasternack enterprises all rights reserved PEM002 rev millimeter wave receiver module operating from 57 ghz to 64 ghz PEM002 cad drawing

▲Up To Search▲

Price & Availability of PEM002

	To Download PEM002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .